HOWEVER
The oboe bears a striking resemblance to the IrDA controller in the Toshiba RISC TMPR3922 chip. The documentation for this chip is available at
http://www.toshiba.com/taec/components/Generic/TMPR3922.shtml or locally
The registers aren't quite in the same places but the following table
should help, for each 32 bit register in the 3922 Risc chip it lists where
corresponding register for each of the four bytes may be found in the oboe
chip.
| 3922 Register and bits | oboe register (relative to port base) |
| $28 bits 7-0 | 0x00 |
| $28 bits 15-8 | 0x01 |
| $2c bits A17-A10 | 0x04 (NOTE 1) |
| $2c bits A25-A18 | 0x05 (NOTE 1) |
| $2c bits A31-A26 | 0x02 (NOTE 1) |
| the remaining bits A9-A0 must be zero (ie the ring must be aligned to a 1k boundary) | |
| $30 bits 7-0 | 0x06 |
| $30 bits 15-8 | 0x07 |
| $34 bits 7-0 | 0x08 |
| $34 bits 15-8 | 0x09 (NOTE 2) |
| $38 bits 7-0 | 0x10 |
| $38 bits 15-8 | 0x11 |
| $3c bits 15-8 | 0x0e (NOTE 3) |
| $40 bits 7-0 | 0x12 |
| $40 bits 15-8 | 0x13 |
| $44 bits 7-0 | 0x14 |
| $44 bits 15-8 | 0x15 |
| $48 bits 7-0 | 0x16 |
| $48 bits 15-8 | 0x17 |
| $4c bits 7-0 | 0x18 |
| $4c bits 15-8 | 0x19 |
| $50 bits 7-0 | 0x1a or 0x1b (Unsure) |
| $50 bits 15-8 | 0x1b or 0x1a (Unsure) |
| $54 bits 7-0 | 0x1d |
| $54 bits 15-8 | 0x1c |
| $5c bits 7-0 | 0xf (NOTE 4) |
| $130 | (NOTE 5) |
| $134 | (NOTE 6) |
Notes:
1. The ring pointer is packed pretty unceremoniusly into the oboe
Oboe Register D7 D6 D5 D4 D3 D2 D1 D0 0x4 A17 A16 A15 A14 A13 A12 A11 A10 0x5 A25 A24 A23 A22 A21 A20 A19 A18 0x2 0 0 A31 A30 A29 A28 A27 A26 2. Toshiba's M$ drivers do a write of 0x1 to 0x9 the docs would suggest 0x8 would be the correct value.
3. This assignment is tenuous at best, register 0xe seems to have bits arranged 0 0 0 R/W R/W R/W R/W R/W if either of the lower two bits are set the chip seems to switch off
4. Bits 7-4 seem to be different 4 seems just to be generic receiver busy flag
5. The IER and ISR have different bit assignments the ISR it at 0x0c and is arranged
D7 D6 D5 D4 D3 D2 D1 D0 TxDone RxDone TxUndr RxOver SipRcv 1 1 1 Interrupts are cleared by writing a 1 to the corresponding bit in the ISR
TxDone indicates that a task in the ring with the interrupt bit set has completed.
RxDone indicated that a receive task (or other specified condition) has occured
TxUndr underflow in Transmit FIFO (PCI bus to busy)
RxOver overflow in Receive FIFO (PCI bus to busy)
SipRcv received serial gap (and also other conditions)6. The IER is as 0xd and has the same bits as the ISR. Interrupts are enabled by writing a 1 to the corresponding bit in the IER.
7. The remaining register 0x6 and 0x3 appear to be reserved parts of 16 or 32 bits registers. The remainder 0xa 0xb 0x1e 0x1f could possibly be (by their behaiour) the Unicast Filter register at $58.
8. While the core obviously expect 32 bit accesses all the M$ driver do 8 bit accesses, infact the miniport ones seem to write and check the 8 bits values many times (why?)